There are some data representation method to store a multi-byte data in a byte addressable memory.
Some types of CPU utilize the little endian method in which low order byte is positioned at the low end of an address, and high order byte is positioned at the high end of an address when storing data of a two-byte length or greater in memory, and the big endian method, which is the reverse. An address in byte units is provided for the data stored in the memory in many cases.
Therefore data of a four-byte length as shown in FIG. 1A, for example, when written into memory as $WWXXYYZZ (where each alphabetic character indicates one digit in hexadecimal), is arranged in little endian as shown in FIG. 1B, and in big endian as shown in FIG. 1C. However, because there is a difference in arrangement in the memory, when two CPUs with different endians exchange data via memory, erroneous data is, of course, transferred.
In particular, in the exchange of control data between a peripheral device and the CPU, it frequently happens that data units of various lengths are made into elements, and data blocks formed from a plurality of data elements are used.
Major problems arise because the arrangements differ according to the length of the data element. For example, if the data length is restricted to two bytes and the width of the data bus is two bytes, the data bus may be divided into two signal line groups of one-byte width and wired so that the low order bytes and the high order bytes are exchanged.
In the case where one-byte length data and four-byte length data units are included, it is clear that transfer cannot be carried out in the correct data sequence. For this reason, in many CPUs the sequence of the data bytes in memory is changed by means of a program. For this reason, an excess of processing time is used in data exchange between peripheral devices, and many problems occur in the interfacing of peripheral devices and CPUs.
Accordingly, there have conventionally been many proposals covering technology for sequencing transferred data.
For example, in an "Endian conversion method" disclosed in Japanese Laid Open Patent Application No. 3-160550 the endian formats for a local processor and a main processor differ, so in the case where data is transferred between the two processors via a common memory, a data swap control section to exchange byte order and a register for storing swap information for word size data are provided between the main processor and the common memory. When data to be swapped is transferred the swap is executed by the data swap control section from a swap instruction set in the register.
In transferring data between the two processors using this conventional technology, the main processor orders a swap operation for communication data with homogeneous data size to ascertain whether or not word data is to be swapped, and the swap operation isn't ordered so that parameter data including various types of data is not swapped.
Specifically, one type of swap exchange is made for data transferred continuously in large volume. However, in this type of technology, when a data structure is transferred which is made up of various data sizes in which byte data, word data, and long word data is mixed, if a swap is made the main processor must issue the swap operation for each individual data unit in turn so that it is impossible to execute high speed data transfer operation.
In addition, in a "Data processing system" disclosed in Japanese Laid Open Patent Application No. 2-141857, a data structure conversion means provided in an interface section for the common bus and the data processing devices and a control register for controlling the method of conversion in a program are provided in a data processing system comprising a plurality of data processing devices linked by a common bus, and the data arrangement structure is sequenced between the data processing devices and the common bus so that processing time is shortened.
However, the data transferred in this system is homogeneous data and there is no indication of the transfer of a mixture of various sizes of data units.
Specifically, the data set in a control register shown in FIG. 1 of the above-mentioned publication is one bit of data, "0" or "1", and is not formed from a plurality of bits. Accordingly, if various sizes of data units are mixed, a plurality of bits is required. This system, therefore, is not capable of transferring a data structure which is made up of a mixture of data units of various sizes.
Also, in a "Data structure conversion method" disclosed in Japanese Laid Open Patent Application No. 63-263524, a data structure conversion device is provided between an external memory device and a main memory device. When data is transferred, the data structure for each data transfer unit is changed in response to a data structure conversion request, and the transfer is then performed.
In this method, a structural conversion is performed by moving data in a record to an indicated address, and a data base vector process is simplified by changing the line up in a predetermined address. However, it is not possible to transfer correctly structured data which includes data elements of various lengths.
As explained above, in a conventional data transfer device which performs data transfer between devices using different endian formats, it is possible to change the structure of data blocks made up of data elements of a uniform length and transfer these data blocks, but it is not possible to change the structure and transfer data blocks which include data elements of various lengths.
Furthermore, when the data is transferred, the structure is changed using a program, or the structure is changed according to an instruction given to each data element in turn, therefore considerable processing time is required to perform such changes so that high speed data transfer becomes a problem.